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» Near-memory Caching for Improved Energy Consumption
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ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
15 years 3 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
86
Voted
ISCA
2002
IEEE
112views Hardware» more  ISCA 2002»
15 years 2 months ago
Drowsy Caches: Simple Techniques for Reducing Leakage Power
On-chip caches represent a sizable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potential...
Krisztián Flautner, Nam Sung Kim, Steven M....
83
Voted
HPCA
2006
IEEE
15 years 3 months ago
Increasing the cache efficiency by eliminating noise
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
Prateek Pujara, Aneesh Aggarwal
WCE
2007
14 years 10 months ago
Modified Energy Efficient Cache Invalidation Algorithm in Mobile Environment
– Maintenance of the cache consistency is a complicated issue in the wireless mobile environment. Caching of frequently accessed data items on the node can reduce the bandwidth r...
S. Sankara Gomathi, S. Krishnamurthi
86
Voted
IWSOC
2003
IEEE
104views Hardware» more  IWSOC 2003»
15 years 2 months ago
Incorporating Pattern Prediction Technique for Energy Efficient Filter Cache Design
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...
Kugan Vivekanandarajah, Thambipillai Srikanthan, S...