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» Near-memory Caching for Improved Energy Consumption
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DCC
2008
IEEE
15 years 1 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...
TSMC
2008
192views more  TSMC 2008»
14 years 11 months ago
AIDOA: An Adaptive and Energy-Conserving Indexing Method for On-Demand Data Broadcasting Systems
Since only a modest improvement in battery lifetime is expected in the next few years, energy conservation is raised as a key factor of the design of mobile devices. In view of th...
Jiun-Long Huang
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
15 years 6 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
CASES
2006
ACM
15 years 5 months ago
Mitigating soft error failures for multimedia applications by selective data protection
With advances in process technology, soft errors (SE) are becoming an increasingly critical design concern. Due to their large area and high density, caches are worst hit by soft ...
Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, N...
HPCA
2009
IEEE
16 years 8 days ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...