983 search results - page 152 / 197 » Negative-Weight Cycle Algorithms |
143
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MICRO
2008
IEEE
16 years 14 days ago
2008
IEEE
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
132
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ARITH
2007
IEEE
16 years 12 days ago
2007
IEEE
The floating point unit of the next generation PowerPC is detailed. It has been tested at over 5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a tech...
152
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DATE
2007
IEEE
16 years 12 days ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
184
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ICRA
2007
IEEE
16 years 11 days ago
2007
IEEE
Abstract— We describe a fast method to relocalise a monocular visual SLAM (Simultaneous Localisation and Mapping) system after tracking failure. The monocular SLAM system stores ...
177
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INFOCOM
2007
IEEE
16 years 11 days ago
2007
IEEE
Abstract—In this paper we address the problem of energyefficient event detection in wireless sensor networks (WSNs). Duty cycling is a fundamental approach to conserving energy i...