983 search results - page 27 / 197 » Negative-Weight Cycle Algorithms |
113
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ARITH
2003
IEEE
15 years 8 months ago
2003
IEEE
We propose an algorithm for modular multiplication/division suitable for VLSI implementation. The algorithm is based on Montgomery’s method for modular multiplication and on the...
110
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ISCAS
2002
IEEE
15 years 8 months ago
2002
IEEE
Delta-sigma modulation for analog-to-digital conversion resolves a number of bits logarithmic in the number of modulation cycles, and linear in modulation order. As an alternative...
117
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CCECE
2009
IEEE
15 years 8 months ago
2009
IEEE
A statistical algorithm was developed for the damage fault diagnosis and prognosis tool and the present work focuses on the experimental validation. The oxide scale growth experim...
138
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ICCAD
2003
IEEE
16 years 11 hour ago
2003
IEEE
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous design, this requires the consideration o...
146
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ICCAD
1999
IEEE
15 years 7 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...