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VLSID
2002
IEEE
119views VLSI» more  VLSID 2002»
16 years 3 months ago
Reducing Library Development Cycle Time through an Optimum Layout Create Flow
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
Rituparna Mandal, Dibyendu Goswami, Arup Dash
SPAA
2003
ACM
15 years 8 months ago
Cycle stealing under immediate dispatch task assignment
We consider the practical problem of task assignment in a server farm, where each arriving job is immediately dispatched to a server in the farm. We look at the benefit of cycle ...
Mor Harchol-Balter, Cuihong Li, Takayuki Osogami, ...
TIP
2008
168views more  TIP 2008»
15 years 3 months ago
A Real-Time Algorithm for the Approximation of Level-Set-Based Curve Evolution
Abstract--In this paper, we present a complete and practical algorithm for the approximation of level-set-based curve evolution suitable for real-time implementation. In particular...
Yonggang Shi, William Clement Karl
ISCC
2003
IEEE
15 years 8 months ago
Pipelined Maximal Size Matching Scheduling Algorithms for CIOQ Switches.
In this paper, we propose new pipelined request-grant-accept (RGA) and request-grant (RG) maximal size matching (MSM) algorithms to achieve speedup in combined input and output qu...
Mei Yang, Si-Qing Zheng
DM
1998
68views more  DM 1998»
15 years 2 months ago
Alternating cycles and trails in 2-edge-coloured complete multigraphs
We consider edge-coloured multigraphs. A trail in such a multigraph is alternating if its successive edges differ in colour. Let G be a 2-edge-coloured complete graph and let M b...
Jørgen Bang-Jensen, Gregory Gutin