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ASPDAC
2004
ACM
97views Hardware» more  ASPDAC 2004»
15 years 8 months ago
A cosynthesis algorithm for application specific processors with heterogeneous datapaths
Abstract- This paper proposes a hardwadsoftware cosynthesis algorithm for processors with heterogeneous registers. Given a CDFG correspondingto an application program and a timing ...
Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa,...
IFIP
1999
Springer
15 years 7 months ago
A Synthesis Algorithm for Modular Design of Pipelined Circuits
: This paper presents a synthesis algorithm for pipelined circuits. The circuit is specified as a collection of independent, looselycoupled modules connected by queues. The synthe...
Maria-Cristina V. Marinescu, Martin C. Rinard
ISCAS
2006
IEEE
106views Hardware» more  ISCAS 2006»
15 years 9 months ago
A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time
—This paper presents a Frequency-Estimation Algorithm for the ADPLL designs instead of traditional binary frequency-search algorithm. With the proposed ADPLL architecture and syn...
Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu
VLDB
1994
ACM
148views Database» more  VLDB 1994»
15 years 7 months ago
Cache Conscious Algorithms for Relational Query Processing
The current main memory (DRAM) access speeds lag far behind CPU speeds. Cache memory, made of static RAM, is being used in today's architectures to bridge this gap. It provid...
Ambuj Shatdal, Chander Kant, Jeffrey F. Naughton
FOCI
2007
IEEE
15 years 9 months ago
Faster Evolutionary Algorithms by Superior Graph Representation
— We present a new representation for individuals in problems that have cyclic permutations as solutions. To demonstrate its usefulness, we analyze a simple randomized local sear...
Benjamin Doerr, Christian Klein, Tobias Storch