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ICIP
2009
IEEE
16 years 4 months ago
Memory-less Bit-plane Coder Architecture For Jpeg2000 With Concurrent Column-stripe Coding
In implementing an efficient block coder for JPEG2000, the memories required for storing the state variables dominate the hardware cost of a block coder. In this paper, we propose...
ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
16 years 9 hour ago
Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications
We propose two new instructions, swperm and sieve, that can be used to efficiently complete an arbitrary bit-level permutation of an n-bit word with or without repetitions. Permut...
John Patrick McGregor, Ruby B. Lee
ACSD
2008
IEEE
102views Hardware» more  ACSD 2008»
15 years 9 months ago
Performing causality analysis by bounded model checking
Synchronous systems can immediately react to the inputs of their environment which may lead to so-called causality cycles between actions and their trigger conditions. Systems wit...
Klaus Schneider, Jens Brandt
SBCCI
2004
ACM
111views VLSI» more  SBCCI 2004»
15 years 8 months ago
A partial reconfigurable architecture for controllers based on Petri nets
Digital Control System in the industry has been used in most of the applications based on expensive Programmable Logical Controllers (PLC). These Systems are, in general, highly c...
Paulo Sérgio B. do Nascimento, Paulo Romero...
DATE
2000
IEEE
140views Hardware» more  DATE 2000»
15 years 7 months ago
Parallel and Distributed VHDL Simulation
This paper presents a methodology for parallel and distributed simulation of VHDL using the PDES (parallel discrete-event simulation) paradigm. To achieve better features and perf...
Dragos Lungeanu, C.-J. Richard Shi