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ICCAD
2002
IEEE
110views Hardware» more  ICCAD 2002»
15 years 12 months ago
Whirlpool PLAs: a regular logic structure and their synthesis
 A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is ...
Fan Mo, Robert K. Brayton
IPPS
2006
IEEE
15 years 9 months ago
Towards an analysis of race carrier conditions in real-time Java
The RTSJ memory model propose a mechanism based on a scope three containing all region-stacks in the system and a reference-counter collector. In order to avoid reference cycles a...
M. Teresa Higuera-Toledano
ICMCS
2005
IEEE
104views Multimedia» more  ICMCS 2005»
15 years 8 months ago
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
Grzegorz Pastuszak
CP
2005
Springer
15 years 8 months ago
Domain Reduction for the Circuit Constraint
Abstract. We present an incomplete filtering algorithm for the circuit constraint. The filter removes redundant values by eliminating nonHamiltonian edges from the associated gra...
Latife Genç Kaya, John N. Hooker
CP
2006
Springer
15 years 6 months ago
A Structural Characterization of Temporal Dynamic Controllability
An important issue for temporal planners is the ability to handle temporal uncertainty. Recent papers have addressed the question of how to tell whether a temporal network is Dynam...
Paul Morris