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94
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ICCD
2008
IEEE
167views Hardware» more  ICCD 2008»
15 years 6 months ago
Exploiting spare resources of in-order SMT processors executing hard real-time threads
— We developed an SMT processor that allows a static WCET analysis of several hard real-time threads and uses the remaining resources for soft or non real-time threads. The analy...
Jörg Mische, Sascha Uhrig, Florian Kluge, The...
RTAS
2008
IEEE
15 years 6 months ago
Optimizing the Implementation of Communication in Synchronous Reactive Models
A fundamental asset of a model-based development process is the capability of providing an automatic implementation of the model that preserves its semantics and, at the same time...
Marco Di Natale, Guoqiang Wang, Alberto L. Sangiov...
RTAS
2008
IEEE
15 years 6 months ago
Using Trace Scratchpads to Reduce Execution Times in Predictable Real-Time Architectures
Instruction scratchpads have been previously suggested as a way to reduce the worst case execution time (WCET) of hard real-time programs without introducing the analysis issues p...
Jack Whitham, Neil C. Audsley
RTCSA
2008
IEEE
15 years 6 months ago
Energy Management for Periodic Real-Time Tasks with Variable Assurance Requirements
Reliability-aware power management (RAPM) schemes, which consider the negative effects of voltage scaling on system reliability, were recently studied to save energy while preserv...
Dakai Zhu, Xuan Qi, Hakan Aydin
99
Voted
AINA
2007
IEEE
15 years 6 months ago
Synthetic Trace-Driven Simulation of Cache Memory
The widening gap between CPU and memory speed has made caches an integral feature of modern highperformance processors. The high degree of configurability of cache memory can requ...
Rahman Hassan, Antony Harris, Nigel P. Topham, Ari...