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GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 3 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
15 years 3 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
CCS
2006
ACM
15 years 3 months ago
TCG inside?: a note on TPM specification compliance
The Trusted Computing Group (TCG) has addressed a new generation of computing platforms employing both supplemental hardware and software with the primary goal to improve the secu...
Ahmad-Reza Sadeghi, Marcel Selhorst, Christian St&...
CMSB
2006
Springer
15 years 3 months ago
Type Inference in Systems Biology
Type checking and type inference are important concepts and methods of programming languages and software engineering. Type checking is a way to ensure some level of consistency, d...
François Fages, Sylvain Soliman
CVPR
2006
IEEE
15 years 3 months ago
Multiple Face Model of Hybrid Fourier Feature for Large Face Image Set
The face recognition system based on the only single classifier considering the restricted information can not guarantee the generality and superiority of performances in a real s...
Wonjun Hwang, Gyu-tae Park, Jong Ha Lee, Seok-Cheo...