49 search results - page 7 / 10 » Neural Compiler Technology for a Parallel Architecture |
163
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IEEEPACT
2008
IEEE
15 years 10 months ago
2008
IEEE
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
110
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DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
With new sophisticated compiler technology, it is possible to schedule distant instructions efficiently. As a consequence, the amount of exploitable instruction level parallelism...
126
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ISCA
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper presents core fusion, a reconfigurable chip multiprocessor (CMP) architecture where groups of fundamentally independent cores can dynamically morph into a larger CPU, ...
129
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EUROPAR
2001
Springer
15 years 8 months ago
2001
Springer
Abstract. In this paper, we address two key trends in the synthesis of implementations for embedded multiprocessors — (1) the increasing importance of managing interprocessor com...
119
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SC
2004
ACM
15 years 9 months ago
2004
ACM
The Merrimac supercomputer uses stream processors and a highradix network to achieve high performance at low cost and low power. The stream architecture matches the capabilities o...