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» Neural Compiler Technology for a Parallel Architecture
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ASAP
2003
IEEE
107views Hardware» more  ASAP 2003»
15 years 9 months ago
Energy Aware Register File Implementation through Instruction Predecode
The register file is a power-hungry device in modern architectures. Current research on compiler technology and computer architectures encourages the implementation of larger dev...
José L. Ayala, Marisa Luisa López-Va...
IPPS
2005
IEEE
15 years 9 months ago
MegaProto: A Low-Power and Compact Cluster for High-Performance Computing
“MegaProto” is a proof-of-concept prototype for our project “Mega-Scale Computing Based on Low-Power Technology and Workload Modeling”, implementing our key idea that a mi...
Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sat...
EDBT
2004
ACM
143views Database» more  EDBT 2004»
16 years 4 months ago
OGSA-DQP: A Service for Distributed Querying on the Grid
OGSA-DQP is a distributed query processor exposed to users as an Open Grid Services Architecture (OGSA)-compliant Grid service. This service supports the compilation and evaluation...
M. Nedim Alpdemir, Arijit Mukherjee, Anastasios Go...
ISCA
1995
IEEE
92views Hardware» more  ISCA 1995»
15 years 7 months ago
A Comparison of Full and Partial Predicated Execution Support for ILP Processors
One can e ectively utilize predicated execution to improve branch handling in instruction-level parallel processors. Although the potential bene ts of predicated execution are hig...
Scott A. Mahlke, Richard E. Hank, James E. McCormi...
142
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CISS
2008
IEEE
15 years 10 months ago
Distributed processing in frames for sparse approximation
—Beyond signal processing applications, frames are also powerful tools for modeling the sensing and information processing of many biological and man-made systems that exhibit in...
Christopher J. Rozell