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CODES
1996
IEEE
15 years 1 months ago
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine
The partitioning of image processing algorithms with a novel hardware/software co-designframework (CoDe-X) is presented in this paper, where a new Xputer-architecture (parallel Ma...
Reiner W. Hartenstein, Jürgen Becker, Rainer ...
FPL
2001
Springer
142views Hardware» more  FPL 2001»
15 years 2 months ago
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs
Field programmable gate arrays (FPGAs) are flexible programmable devices that are used in a wide variety of applications such as network routing, signal processing, pattern recogni...
Bryan S. Goda, Russell P. Kraft, Steven R. Carloug...
ISCAS
2003
IEEE
129views Hardware» more  ISCAS 2003»
15 years 2 months ago
SONICmole: a debugging environment for the UltraSONIC reconfigurable computer
Reconfigurable Computers based on a combination of conventional microprocessors and Field Programmable Gate Arrays (FPGAs) presents new challenges to designers. Debugging on such ...
Theerayod Wiangtong, Chun Te Ewe, Peter Y. K. Cheu...
CORR
2011
Springer
209views Education» more  CORR 2011»
14 years 4 months ago
Aneka Cloud Application Platform and Its Integration with Windows Azure
Aneka is an Application Platform-as-a-Service (Aneka PaaS) for Cloud Computing. It acts as a framework for building customized applications and deploying them on either public or ...
Yi Wei, Karthik Sukumar, Christian Vecchiola, Dile...
FPL
2003
Springer
74views Hardware» more  FPL 2003»
15 years 2 months ago
Reconfigurable Circuits Using Hybrid Hall Effect Devices
Abstract. Hybrid Hall effect (HHE) devices are a new class of reconfigurable logic devices that incorporate ferromagnetic elements to deliver nonvolatile operation. A single HHE de...
Steve Ferrera, Nicholas P. Carter