Sciweavers

8441 search results - page 204 / 1689
» New Architectures for Vision
Sort
View
ASPDAC
1995
ACM
77views Hardware» more  ASPDAC 1995»
15 years 9 months ago
A scheduling algorithm for synthesis of bus-partitioned architectures
- Due to efficient interconnect structure and internal parallelism bus-partitioned architectures are very beneficial for sub-micron chip design. This paper presents a new approach ...
Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi T...
GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
15 years 6 months ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...
ISI
2004
Springer
15 years 11 months ago
The Architecture of the Cornell Knowledge Broker
Intelligence applications have to process massive amounts of data in order to extract relevant information. This includes archived historical data as well as continuously arriving ...
Alan J. Demers, Johannes Gehrke, Mirek Riedewald
ISCAS
2002
IEEE
91views Hardware» more  ISCAS 2002»
15 years 11 months ago
Pipelined RLS adaptive architecture using relaxed Givens rotations (RGR)
In this paper, we focus on developing a new relaxed Givens rotations (RGR)-RLS algorithm and the corresponding RGR-RLS systolic array. The resulting algorithm and architecture pos...
Lan-Da Van, Chih-Hong Chang
CODES
2000
IEEE
15 years 10 months ago
Extended design reuse trade-offs in hardware-software architecture mapping
In the design of embedded systems-on-chip, the success of a product generation depends on the exibility to accommodate future design changes. This requirement in uences the hardwa...
Frederik Vermeulen, Francky Catthoor, Diederik Ver...