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ICNP
2005
IEEE
15 years 3 months ago
Robust Multiclass Signaling Overload Control
We propose multi-class signaling overload control algorithms, for telecommunication switches, that are robust against different input traffic patterns and system upgrades. In ord...
Sneha Kumar Kasera, José Pinheiro, Catherin...
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
15 years 3 months ago
Virtually Pipelined Network Memory
We introduce virtually-pipelined memory, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput eve...
Banit Agrawal, Timothy Sherwood
TDSC
2010
111views more  TDSC 2010»
14 years 7 months ago
Using Underutilized CPU Resources to Enhance Its Reliability
—Soft errors (or Transient faults) are temporary faults that arise in a circuit due to a variety of internal noise and external sources such as cosmic particle hits. Though soft ...
Avi Timor, Avi Mendelson, Yitzhak Birk, Neeraj Sur...
CSMR
2004
IEEE
15 years 1 months ago
Supporting Architectural Restructuring by Analyzing Feature Models
In order to lower the risk, reengineering projects aim at high reuse rates. Therefore, tasks like architectural restructuring have to be performed in a way that developed new syst...
Ilian Pashov, Matthias Riebisch, Ilka Philippow
TVLSI
2008
108views more  TVLSI 2008»
14 years 9 months ago
Unified Convolutional/Turbo Decoder Design Using Tile-Based Timing Analysis of VA/MAP Kernel
To satisfy the advanced forward-error-correction (FEC) standards, in which the Convolutional code and Turbo code may co-exit, a prototype design of a unified Convolutional/Turbo de...
Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu