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LPAR
2005
Springer
15 years 5 months ago
Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination
Separation logic is a subset of the quantifier-free first order logic. It has been successfully used in the automated verification of systems that have large (or unbounded) inte...
Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti G...
SMA
2003
ACM
154views Solid Modeling» more  SMA 2003»
15 years 5 months ago
Discretization of functionally based heterogeneous objects
The presented approach to discretization of functionally defined heterogeneous objects is oriented towards applications associated with numerical simulation procedures, for exampl...
Elena Kartasheva, Valery Adzhiev, Alexander A. Pas...
ASPDAC
1998
ACM
101views Hardware» more  ASPDAC 1998»
15 years 4 months ago
An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits
ABSTRACT - This paper presents a new design flow, FPDSiMPA, and a set of techniques for synthesizing high-performance sub-half micron logic circuits. FPD-SiMPA consists of logic p...
Jinan Lou, Amir H. Salek, Massoud Pedram
DAC
2010
ACM
15 years 3 months ago
An AIG-Based QBF-solver using SAT for preprocessing
In this paper we present a solver for Quantified Boolean Formulas (QBFs) which is based on And-Inverter Graphs (AIGs). We use a new quantifier elimination method for AIGs, which...
Florian Pigorsch, Christoph Scholl
CSR
2008
Springer
15 years 1 months ago
Comparing Universal Covers in Polynomial Time
The universal cover TG of a connected graph G is the unique (possible infinite) tree covering G, i.e., that allows a locally bijective homomorphism from TG to G. Universal covers h...
Jirí Fiala, Daniël Paulusma