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» New Techniques for Algorithm Portfolio Design
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ISPD
2012
ACM
283views Hardware» more  ISPD 2012»
13 years 7 months ago
Low-power gated bus synthesis for 3d ic via rectilinear shortest-path steiner graph
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-H...
DEXA
2008
Springer
117views Database» more  DEXA 2008»
15 years 1 months ago
Space-Partitioning-Based Bulk-Loading for the NSP-Tree in Non-ordered Discrete Data Spaces
Properly-designed bulk-loading techniques are more efficient than the conventional tuple-loading method in constructing a multidimensional index tree for a large data set. Although...
Gang Qian, Hyun-Jeong Seok, Qiang Zhu, Sakti Prama...
ICES
2000
Springer
140views Hardware» more  ICES 2000»
15 years 3 months ago
Evolving Cellular Automata for Self-Testing Hardware
Testing is a key issue in the design and production of digital circuits: the adoption of BIST (Built-In Self-Test) techniques is increasingly popular, but requires efficient algori...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
NIME
2004
Springer
93views Music» more  NIME 2004»
15 years 5 months ago
On the Choice of Mappings Based On Geometric Properties
The choice of mapping strategies to effectively map controller variables to sound synthesis algorithms is examined. Specifically, we look at continuous mappings that have a geom...
Doug Van Nort, Marcelo M. Wanderley, Philippe Depa...
ISCAS
1993
IEEE
125views Hardware» more  ISCAS 1993»
15 years 4 months ago
A VLSI Implementation of a Cascade Viterbi Decoder with Traceback
- A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read poin...
Gennady Feygin, Paul Chow, P. Glenn Gulak, John Ch...