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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
15 years 6 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
NETWORKING
2000
14 years 10 months ago
Spare Capacity Planning for Survivable Mesh Networks
Abstract. The design of survivable mesh based STM networks has received considerable attention in recent years and is a complex multiconstraint optimization problem. In this paper,...
Adel Al-Rumaih, David Tipper, Yu Liu, Bryan A. Nor...
PPSN
1992
Springer
15 years 1 months ago
Hyperplane Annealing and Activator-Inhibitor-Systems
This paper introduces a new optimization technique called hyperplane annealing. It is similar to the mean field annealing approach to combinatorial optimization. Both annealing te...
Thomas Laußermair
CPAIOR
2010
Springer
15 years 2 months ago
Upper Bounds on the Number of Solutions of Binary Integer Programs
We present a new method to compute upper bounds of the number of solutions of binary integer programming (BIP) problems. Given a BIP, we create a dynamic programming (DP) table for...
Siddhartha Jain, Serdar Kadioglu, Meinolf Sellmann
ICCV
2005
IEEE
15 years 3 months ago
Space-Time Scene Manifolds
The space of images is known to be a non-linear subspace that is difficult to model. This paper derives an algorithm that walks within this space. We seek a manifold through the ...
Yonatan Wexler, Denis Simakov