Sciweavers

357 search results - page 32 / 72
» No new wires
Sort
View
DAC
2003
ACM
16 years 1 months ago
An O(nlogn) time algorithm for optimal buffer insertion
The classic algorithm for optimal buffer insertion due to van Ginneken has time and space complexity O(n2 ), where n is the number of possible buffer positions. We present a new a...
Weiping Shi, Zhuo Li
VLSID
2006
IEEE
153views VLSI» more  VLSID 2006»
16 years 25 days ago
An Asynchronous Interconnect Architecture for Device Security Enhancement
We present a new style of long-distance, on-chip interconnect, based loosely on the asynchronous GasP architecture. It has a number of advantages over conventional designs, the mo...
Simon Hollis, Simon W. Moore
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
15 years 9 months ago
Placement Driven Retiming with a Coupled Edge Timing Model
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
Ingmar Neumann, Wolfgang Kunz
79
Voted
WOWMOM
2009
ACM
144views Multimedia» more  WOWMOM 2009»
15 years 7 months ago
A CARMEN mesh experience: deployment and results
When there is no wired connectivity, wireless mesh networks (WMNs) can provide Internet access with lower cost and greater flexibility than traditional approaches. This has motiv...
Pablo Serrano, Antonio de la Oliva, Carlos Jesus B...
93
Voted
VLSID
2007
IEEE
131views VLSI» more  VLSID 2007»
15 years 6 months ago
A Placement Methodology for Robust Clocking
As the VLSI technology scales towards the nanometer regime, circuit performance is increasingly affected by variations. These variations need to be considered at an early stage in...
Ganesh Venkataraman, Jiang Hu