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111
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CORR
2008
Springer
135views Education» more  CORR 2008»
15 years 2 months ago
A DCCP Congestion Control Mechanism for Wired- cum-Wireless Environments
Existing transport protocols, be it TCP, SCTP or DCCP, do not provide an efficient congestion control mechanism for heterogeneous wired-cum-wireless networks. Solutions involving i...
Ijaz Haider Naqvi, Tanguy Pérennou
124
Voted
VLSISP
2008
108views more  VLSISP 2008»
15 years 1 months ago
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
Edmund Lee, Guy Lemieux, Shahriar Mirabbasi
107
Voted
VLSID
2002
IEEE
120views VLSI» more  VLSID 2002»
16 years 2 months ago
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
We describe a new algorithm for floorplan evaluation using timing-driven buffered routing according to a prescribed buffer site map. Specifically, we describe a provably good mult...
Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoi...
93
Voted
ASPDAC
2006
ACM
97views Hardware» more  ASPDAC 2006»
15 years 7 months ago
Wire sizing with scattering effect for nanoscale interconnection
—For nanoscale interconnection, the scattering effect will soon become prominent due to scaling. It will increase the effective resistivity and thus interconnection delay signifi...
Sean X. Shi, David Z. Pan
139
Voted
DAC
2006
ACM
15 years 7 months ago
Clock buffer and wire sizing using sequential programming
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
Matthew R. Guthaus, Dennis Sylvester, Richard B. B...