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» Noise margin analysis for dynamic logic circuits
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ISCAS
2003
IEEE
83views Hardware» more  ISCAS 2003»
15 years 2 months ago
Low-noise low-power allpole active-RC filters minimizing resistor level
The design procedure of 2nd - and 3rd -order low-sensitivity lowpower allpole active resistance-capacitance (RC) filters, using the impedance tapering design method has already be...
Drazen Jurisic, George S. Moschytz, Neven Mijat
ISPD
2003
ACM
151views Hardware» more  ISPD 2003»
15 years 2 months ago
Capturing crosstalk-induced waveform for accurate static timing analysis
We propose a method to capture crosstalk-induced noisy waveform for crosstalk-aware static timing analysis. The effects of capacitive coupling noise on timing are conventionally m...
Masanori Hashimoto, Yuji Yamada, Hidetoshi Onodera
VLSID
2009
IEEE
119views VLSI» more  VLSID 2009»
15 years 10 months ago
Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems
Abstract-- Single-ended static random access memory (SESRAM) is well known for their tremendous potential of low active power and leakage dissipations. In this paper, we present a ...
Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhi...
DAC
2001
ACM
15 years 10 months ago
Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation
In this paper, we present a new technique for the e cient dynamic detection and removal of inactive clauses, i.e. clauses that do not a ect the solutions of interest of a Boolean ...
Aarti Gupta, Anubhav Gupta, Zijiang Yang, Pranav A...
ICCAD
2009
IEEE
132views Hardware» more  ICCAD 2009»
14 years 7 months ago
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior
Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to ...
Lu Wan, Deming Chen