69 search results - page 11 / 14 » Noise margin analysis for dynamic logic circuits |
ISQED
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents a methodology for accurate propagation of delay information through a gate for the purpose of static timing analysis (STA) in the presence of noise. Convention...
TCAD
2002
14 years 9 months ago
2002
We develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupli...
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ICCAD
1997
IEEE
15 years 1 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
With increasing aggregate off-chip bandwidths exceeding terabits/second (Tb/s), the power dissipation is a serious design consideration. Additionally, design of I/O links is const...
TC
2011
14 years 4 months ago
2011
—Mounting concerns over variability, defects and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signa...