69 search results - page 12 / 14 » Noise margin analysis for dynamic logic circuits |
CHES
2006
Springer
15 years 1 months ago
2006
Springer
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
TVLSI
2008
14 years 9 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
DSD
2007
IEEE
15 years 3 months ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
ISQED
2003
IEEE
15 years 2 months ago
2003
IEEE
Abstract- This paper presents a detailed empirical study and analytical derivation of voltage wave-form and energy dissipation of global lines driven by CMOS drivers. It is shown t...
DAC
2009
ACM
15 years 4 months ago
2009
ACM
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...