69 search results - page 4 / 14 » Noise margin analysis for dynamic logic circuits |
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
Nanometer circuits are becoming increasingly susceptible to soft-errors due to alpha-particle and atmospheric neutron strikes as device scaling reduces node capacitances and suppl...
TODAES
2002
14 years 9 months ago
2002
ct Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes an assumption that all aggressing nets can simultaneousl...
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
— A new low voltage swing circuit technique based on a dual threshold voltage CMOS technology is presented in this paper for simultaneously reducing active and standby mode power...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
Negative bias temperature instability (NBTI) in MOSFETs is one of the major reliability challenges in nano-scale technology. This paper presents an efficient technique to characte...
DAC
1998
ACM
15 years 1 months ago
1998
ACM
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...