69 search results - page 6 / 14 » Noise margin analysis for dynamic logic circuits |
114
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ICCAD
2008
IEEE
15 years 8 months ago
2008
IEEE
— Perturbation Projection Vector (PPV) is an established technique for oscillator phase noise analysis; However, the PPV method significantly loses accuracy when circuits have l...
137
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ICCAD
1996
IEEE
15 years 6 months ago
1996
IEEE
The analysis of CMOS VLSI circuit switching current has become an increasingly important and difficult task from both a VLSI design and simulation software perspective. This paper...
111
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ICCAD
2008
IEEE
15 years 8 months ago
2008
IEEE
— Dynamic power noises may not only degrade the circuit performance but also reduce the noise margin which may result in the functional errors in integrated circuit. Decoupling c...
125
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ICCD
2004
IEEE
15 years 10 months ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...
109
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FPL
2006
Springer
15 years 5 months ago
2006
Springer
FPGA devices exhibit manufacturing variability. Device ratings and Timing margins are typically used in order to cope with inter-device and intra-device variability respectively. ...