69 search results - page 7 / 14 » Noise margin analysis for dynamic logic circuits |
VTS
2005
IEEE
15 years 3 months ago
2005
IEEE
Nanometer circuits are highly susceptible to soft errors generated by alpha-particle or atmospheric neutron strikes to circuit nodes. The reasons for the high susceptibility are t...
TVLSI
2010
14 years 4 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
69
Voted
ASYNC
1999
IEEE
15 years 1 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
ISQED
2003
IEEE
15 years 2 months ago
2003
IEEE
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...
DAC
2007
ACM
15 years 10 months ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...