69 search results - page 8 / 14 » Noise margin analysis for dynamic logic circuits |
GLVLSI
2002
IEEE
15 years 2 months ago
2002
IEEE
A low swing domino logic technique is proposed to decrease power consumption without sacrificing noise immunity. With the proposed low swing domino logic circuit technique, active...
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
83
Voted
GLVLSI
2005
IEEE
15 years 3 months ago
2005
IEEE
Switching model captures the data-driven uncertainty in logic circuits in a comprehensive probabilistic framework. Switching is a critical factor that influences dynamic, active ...
BIOCOMP
2007
14 years 11 months ago
2007
Background: Genetic regulatory networks (GRN) can be described by differential equations with SUM logic which has been found in many natural systems. Identification of the network...
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
— Modern sub-micron VLSI designs include huge power grids that are required to distribute large amounts of current, at increasingly lower voltages. The resulting voltage drop on ...