69 search results - page 9 / 14 » Noise margin analysis for dynamic logic circuits |
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
Device scaling such as reduced oxide thickness and high electric field has given rise to various reliability concerns. One such growing issue of concern is the degradation of PMOS...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— Accurate estimation of worst-case crosstalk effects is critical for a realistic estimation of the worst-case behavior of deep sub-micron circuits. Crosstalk analysis models usu...
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Substantial increase in leakage current and threshold voltage fluctuations are making design of robust wide fan-in dynamic gates a challenging task. Traditionally, a PMOS keeper t...
AB
2007
Springer
15 years 3 months ago
2007
Springer
Abstract. In 1973 R. Thomas introduced a logical approach to modeling and analysis of bioregulatory networks. Given a set of Boolean functions describing the regulatory interaction...