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» Noise-tolerant dynamic circuit design
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VLSID
2003
IEEE
103views VLSI» more  VLSID 2003»
15 years 10 months ago
Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
PATMOS
2005
Springer
15 years 3 months ago
Design of Variable Input Delay Gates for Low Dynamic Power Circuits
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bush...
ASPDAC
2004
ACM
102views Hardware» more  ASPDAC 2004»
15 years 1 months ago
A dynamic element matching circuit for multi-bit delta-sigma modulators
Abstract-A 30k-gate dynamic element matching circuit for bandpass modulators with a 4-bit quantizer is designed by using 0.35-
Ryozo Katoh, Shin-ya Kobayashi, Takao Waho