325 search results - page 31 / 65 » Non-uniform Instruction Scheduling |
DAC
1995
ACM
15 years 4 months ago
1995
ACM
—We address the problem of code optimization for embedded DSP microprocessors. Such processors (e.g., those in the TMS320 series) have highly irregular datapaths, and conventiona...
87
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RTSS
1999
IEEE
15 years 4 months ago
1999
IEEE
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
ISSS
1995
IEEE
15 years 4 months ago
1995
IEEE
This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been dev...
107
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RTSS
2002
IEEE
15 years 5 months ago
2002
IEEE
Simultaneous multithreading (SMT) improves processor throughput by processing instructions from multiple threads each cycle. This is the first work to explore soft real-time sche...
112
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APCSAC
2005
IEEE
15 years 6 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...