325 search results - page 34 / 65 » Non-uniform Instruction Scheduling |
93
Voted
CONCURRENCY
2006
15 years 17 days ago
2006
To keep up with a large degree of instruction level parallelism (ILP), the Itanium 2 cache systems use a complex organization scheme: load/store queues, banking and interleaving. ...
142
Voted
IEEEPACT
2002
IEEE
15 years 5 months ago
2002
IEEE
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
121
Voted
TCAD
2002
15 years 4 days ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
104
Voted
HPCA
1996
IEEE
15 years 4 months ago
1996
IEEE
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
124
Voted
ISCAS
1999
IEEE
15 years 4 months ago
1999
IEEE
The energy usage of computer systems is becoming important, especially for portablebattery-operated applications and embedded systems. A significant reduction in the energy consum...