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ICCD
2002
IEEE
228views Hardware» more  ICCD 2002»
15 years 9 months ago
JMA: The Java-Multithreading Architecture for Embedded Processors
Embedded processors are increasingly deployed in applications requiring high performance with good real-time characteristics whilst being low power. Parallelism has to be extracte...
Panit Watcharawitch, Simon W. Moore
DATE
2007
IEEE
105views Hardware» more  DATE 2007»
15 years 6 months ago
Instruction-set customization for real-time embedded systems
Application-specific customization of the instruction set helps embedded processors achieve significant performance and power efficiency. In this paper, we explore customizatio...
Huynh Phung Huynh, Tulika Mitra
102
Voted
RELMICS
2005
Springer
15 years 6 months ago
Control-Flow Semantics for Assembly-Level Data-Flow Graphs
Abstract. As part of a larger project, we have built a declarative assembly language that enables us to specify multiple code paths to compute particular quantities, giving the ins...
Wolfram Kahl, Christopher Kumar Anand, Jacques Car...
91
Voted
PPL
2006
81views more  PPL 2006»
15 years 13 days ago
Microthreading a Model for Distributed Instruction-level Concurrency
This paper analyses the micro-threaded model of concurrency making comparisons with both data and instruction-level concurrency. The model is fine grain and provides synchronisati...
Chris R. Jesshope
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
14 years 4 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...