325 search results - page 37 / 65 » Non-uniform Instruction Scheduling |
85
Voted
DAC
2006
ACM
16 years 1 months ago
2006
ACM
Design space exploration during high level synthesis is often conducted through ad-hoc probing of the solution space using some scheduling algorithm. This is not only time consumi...
102
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INFOCOM
2002
IEEE
15 years 5 months ago
2002
IEEE
—To provide flexibility in deploying new protocols and services, general-purpose processing engines are being placed in the datapath of routers. Such network processors are typi...
72
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INTERFACES
2008
15 years 15 days ago
2008
: The ballroom dancing showcases at Fred Astaire East Side Dance Studio in Manhattan are held at least twice a year and provide the students with an environment for socializing, pr...
108
Voted
ICASSP
2008
IEEE
15 years 7 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
93
Voted
PLDI
1996
ACM
15 years 4 months ago
1996
ACM
High performance compilers increasingly rely on accurate modeling of the machine resources to efficiently exploit the instruction level parallelism of an application. In this pape...