325 search results - page 38 / 65 » Non-uniform Instruction Scheduling |
103
Voted
DATE
2008
IEEE
15 years 7 months ago
2008
IEEE
Modern embedded CPU systems rely on a growing number of software features, but this growth increases the memory footprint and increases the need for efficient instruction and data...
137
Voted
HPCA
1996
IEEE
15 years 4 months ago
1996
IEEE
We have investigated the register file requirements of dynamically scheduled processors using register renaming and dispatch queues running the SPEC92 benchmarks. We looked at pro...
112
Voted
RTAS
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper discusses an approach for supporting soft realtime periodic tasks in Linux on performance asymmetric multicore platforms (AMPs). Such architectures consist of a large n...
138
click to vote
HPCA
2005
IEEE
16 years 26 days ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
108
Voted
ISLPED
2006
ACM
15 years 6 months ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...