325 search results - page 3 / 65 » Non-uniform Instruction Scheduling |
99
Voted
CGO
2004
IEEE
15 years 2 months ago
2004
IEEE
Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an...
MICRO
2003
IEEE
15 years 3 months ago
2003
IEEE
Ensuring back-to-back execution of dependent instructions in a conventional out-of-order processor requires scheduling logic that wakes up and selects instructions at the same rat...
DAC
1994
ACM
15 years 2 months ago
1994
ACM
We present a systematic approach to synthesize an instruction set such that the given application software can be efficiently mapped to a parameterized, pipelined microarchitectur...
80
Voted
GLVLSI
2006
IEEE
15 years 4 months ago
2006
IEEE
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...
94
Voted
PLDI
1995
ACM
15 years 1 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...