325 search results - page 45 / 65 » Non-uniform Instruction Scheduling |
118
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CC
2003
Springer
15 years 5 months ago
2003
Springer
Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at firs...
111
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IEEEPACT
2000
IEEE
15 years 4 months ago
2000
IEEE
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...
122
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CC
2006
Springer
15 years 4 months ago
2006
Springer
Abstract. Alias analysis, traditionally performed statically, is unsuited for a dynamic binary translator (DBT) due to incomplete control-flow information and the high complexity o...
IPPS
2010
IEEE
14 years 10 months ago
2010
IEEE
We address the design of algorithms for multicores that are oblivious to machine parameters. We propose HM, a multicore model consisting of a parallel shared-memory machine with hi...
ICPP
2008
IEEE
15 years 7 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...