325 search results - page 59 / 65 » Non-uniform Instruction Scheduling |
103
Voted
MICRO
2005
IEEE
15 years 6 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
MICRO
2003
IEEE
15 years 5 months ago
2003
IEEE
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
ASPLOS
2010
ACM
15 years 7 months ago
2010
ACM
A large number of user requests execute (often concurrently) within a server system. A single request may exhibit fluctuating hardware characteristics (such as instruction comple...
104
Voted
IPPS
2006
IEEE
15 years 6 months ago
2006
IEEE
The industry is rapidly moving towards the adoption of Chip Multi-Processors (CMPs) of Simultaneous MultiThreaded (SMT) cores for general purpose systems. The most prominent use o...
110
click to vote
ICLP
2005
Springer
15 years 6 months ago
2005
Springer
We present a methodology for the modeling of complex program behavior in CLP. In the first part we present an informal description about how to represent a system in CLP. At its ...