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» Nonlinear array layouts for hierarchical memory systems
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ISLPED
1995
ACM
112views Hardware» more  ISLPED 1995»
15 years 1 months ago
Ultra-low-power analog associative memory core using flash-EEPROM-based programmable capacitors
Analog techniques can lead to ultra-efficient computational systems when applied to the right applications. The problem of associative memory is well suited to array-based analog ...
Alan Kramer, Roberto Canegallo, Mauro Chinosi, D. ...
CASES
2003
ACM
15 years 2 months ago
Exploiting bank locality in multi-bank memories
Bank locality can be defined as localizing the number of load/store accesses to a small set of memory banks at a given time. An optimizing compiler can modify a given input code t...
Guilin Chen, Mahmut T. Kandemir, Hendra Saputra, M...
81
Voted
CODES
2007
IEEE
15 years 3 months ago
Locality optimization in wireless applications
There is a strong need now for compilers of embedded systems to find effective ways of optimizing series of loop-nests, wherein majority of the memory references occur in the fo...
Javed Absar, Min Li, Praveen Raghavan, Andy Lambre...
CDES
2008
90views Hardware» more  CDES 2008»
14 years 11 months ago
Nanocompilation for the Cell Matrix Architecture
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
Thomas Way, Rushikesh Katikar, Ch. Purushotham
JCDL
2004
ACM
116views Education» more  JCDL 2004»
15 years 2 months ago
Lost in memories: interacting with photo collections on PDAs
We developed two browsers to support large personal photo collections on PDAs. Our first browser is based on a traditional, folder-based layout that utilizes either the user’s m...
Susumu Harada, Mor Naaman, Yee Jiun Song, QianYing...