204 search results - page 20 / 41 » Nonuniform Banking for Reducing Memory Energy Consumption |
57
Voted
MICRO
2006
IEEE
15 years 3 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
104
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CODES
2005
IEEE
14 years 11 months ago
2005
IEEE
Caches may consume half of a microprocessor’s total power and cache misses incur accessing off-chip memory, which is both time consuming and energy costly. Therefore, minimizing...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
This paper presents a scheme to combine memory and power management for achieving better energy reduction. Our method periodically adjusts the size of physical memory and the time...
EJWCN
2010
14 years 4 months ago
2010
Wireless sensor networks are often required to provide event miss-ratio assurance for a given event type. To meet such assurances along with minimum energy consumption, this paper ...
ISCA
2006
IEEE
15 years 3 months ago
2006
IEEE
Level one cache normally resides on a processor’s critical path, which determines the clock frequency. Directmapped caches exhibit fast access time but poor hit rates compared w...