204 search results - page 25 / 41 » Nonuniform Banking for Reducing Memory Energy Consumption |
ISHPC
2003
Springer
15 years 2 months ago
2003
Springer
Abstract. In SMT processors several threads run simultaneously to increase available ILP, sharing but competing for resources. The instruction fetch policy plays a key role, determ...
BTW
2009
Springer
15 years 4 months ago
2009
Springer
Abstract: Green computing or energy saving when processing information is primarily considered a task of processor development. We, however, advocate that a holistic approach is ne...
70
Voted
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
102
click to vote
ASPLOS
2010
ACM
15 years 29 days ago
2010
ACM
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
70
Voted
SAC
2004
ACM
15 years 3 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...