129 search results - page 18 / 26 » Novel Design Methodology for High-Performance XOR-XNOR Circu... |
ASPDAC
2012
ACM
13 years 7 months ago
2012
ACM
With technology scaling, integrated circuits behave more unpredictably due to process variation, environmental changes and aging effects. Various variation-aware and adaptive desi...
91
Voted
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
DAC
2007
ACM
16 years 20 days ago
2007
ACM
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
DAC
2009
ACM
15 years 3 months ago
2009
ACM
Structured ASICs have recently emerged as an exciting alternative to ASIC or FPGA design style as they provide a new trade-off between the high performance of ASIC design and low ...
89
Voted
DATE
2009
IEEE
15 years 6 months ago
2009
IEEE
—In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthe...