138 search results - page 11 / 28 » Novel architecture for loop acceleration: a case study |
93
Voted
CF
2009
ACM
15 years 4 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
ICFP
2008
ACM
15 years 9 months ago
2008
ACM
Command-oriented functional programs are currently structured in an ad hoc way that makes the development of multiple userinterfaces difficult and error prone, and makes it diffic...
ASAP
2004
IEEE
15 years 1 months ago
2004
IEEE
We describe a general-purpose processor architecture for accelerating public-key computations on server systems that demand high performance and flexibility to accommodate large n...
SIPS
2007
IEEE
15 years 3 months ago
2007
IEEE
Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for ...
FPL
2004
Springer
15 years 2 months ago
2004
Springer
ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconf...