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» Novel architecture for loop acceleration: a case study
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CORR
2006
Springer
112views Education» more  CORR 2006»
14 years 9 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
84
Voted
CASES
2009
ACM
15 years 4 months ago
An accelerator-based wireless sensor network processor in 130nm CMOS
Networks of ultra-low-power nodes capable of sensing, computation, and wireless communication have applications in medicine, science, industrial automation, and security. Over the...
Mark Hempstead, Gu-Yeon Wei, David Brooks
86
Voted
SOFTVIS
2010
ACM
14 years 7 months ago
Visual comparison of software architectures
Reverse engineering methods produce different descriptions of software architectures. In this work we analyze and define the task of exploring and comparing these descriptions. ...
Fabian Beck, Stephan Diehl
EIT
2009
IEEE
15 years 4 months ago
System-level memory modeling for bus-based memory architecture exploration
—System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we p...
Zhongbo Cao, Ramon Mercado, Diane T. Rover
AHS
2007
IEEE
251views Hardware» more  AHS 2007»
15 years 1 months ago
System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design
In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity...
Ali Ahmadinia, Balal Ahmad, Tughrul Arslan