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ARC
2007
Springer
150views Hardware» more  ARC 2007»
15 years 1 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
CGO
2004
IEEE
15 years 1 months ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
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EMSOFT
2006
Springer
15 years 1 months ago
A hierarchical coordination language for interacting real-time tasks
We designed and implemented a new programming language called Hierarchical Timing Language (HTL) for hard realtime systems. Critical timing constraints are specified within the la...
Arkadeb Ghosal, Alberto L. Sangiovanni-Vincentelli...
AAAI
2008
14 years 12 months ago
Diagnosing Faults in Electrical Power Systems of Spacecraft and Aircraft
Electrical power systems play a critical role in spacecraft and aircraft, and they exhibit a rich variety of failure modes. This paper discusses electrical power system fault diag...
Ole J. Mengshoel, Adnan Darwiche, Keith Cascio, Ma...
ICFP
2010
ACM
14 years 10 months ago
Scrapping your inefficient engine: using partial evaluation to improve domain-specific language implementation
Partial evaluation aims to improve the efficiency of a program by specialising it with respect to some known inputs. In this paper, we show that partial evaluation can be an effec...
Edwin Brady, Kevin Hammond