The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
We designed and implemented a new programming language called Hierarchical Timing Language (HTL) for hard realtime systems. Critical timing constraints are specified within the la...
Arkadeb Ghosal, Alberto L. Sangiovanni-Vincentelli...
Electrical power systems play a critical role in spacecraft and aircraft, and they exhibit a rich variety of failure modes. This paper discusses electrical power system fault diag...
Ole J. Mengshoel, Adnan Darwiche, Keith Cascio, Ma...
Partial evaluation aims to improve the efficiency of a program by specialising it with respect to some known inputs. In this paper, we show that partial evaluation can be an effec...