20 search results - page 2 / 4 » OS-aware tuning: improving instruction cache energy efficien... |
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
High power consumption and low energy efficiency have become significant impediments to future performance improvements in modern microprocessors. This paper contributes to the so...
WSC
1997
13 years 7 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
GLVLSI
2010
IEEE
13 years 8 months ago
2010
IEEE
Loop caches provide an effective method for decreasing memory hierarchy energy consumption by storing frequently executed code in a more energy efficient structure than the level ...
CASES
2007
ACM
13 years 10 months ago
2007
ACM
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
HIPEAC
2010
Springer
13 years 8 months ago
2010
Springer
Abstract. Customizable processors augmented with application-specific Instruction Set Extensions (ISEs) have begun to gain traction in recent years. The most effective ISEs include...