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ISCA
2002
IEEE
159views Hardware» more  ISCA 2002»
15 years 2 months ago
Avoiding Initialization Misses to the Heap
This paper investigates a class of main memory accesses (invalid memory traffic) that can be eliminated altogether. Invalid memory traffic is real data traffic that transfers inva...
Jarrod A. Lewis, Mikko H. Lipasti, Bryan Black
INFOCOM
2009
IEEE
15 years 4 months ago
To Cache or Not To Cache?
—We address cooperative caching in mobile ad hoc networks where information is exchanged in a peer-to-peer fashion among the network nodes. Our objective is to devise a fully-dis...
Marco Fiore, Francesco Mininni, Claudio Casetti, C...
JTRES
2010
ACM
14 years 9 months ago
WCET driven design space exploration of an object cache
In order to guarantee that real-time systems meet their timing specification, static execution time bounds need to be calculated. Not considering execution time predictability led...
Benedikt Huber, Wolfgang Puffitsch, Martin Schoebe...
WSC
1997
14 years 10 months ago
Model-Driven Simulation of World-Wide-Web Cache Policies
The World Wide Web (WWW) has experienced a dramatic increase in popularity since 1993. Many reports indicate that its growth will continue at an exponential rate. This growth has ...
Ying Shi, Edward Watson, Ye-Sho Chen
VLDB
2007
ACM
119views Database» more  VLDB 2007»
15 years 9 months ago
Path and cache conscious prefetching (PCCP)
Main memory cache performance continues to play an important role in determining the overall performance of object-oriented, object-relational and XML databases. An effective metho...
Zhen He, Alonso Marquez