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FPGA
2010
ACM
209views FPGA» more  FPGA 2010»
16 years 1 months ago
FPGA power reduction by guarded evaluation
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...
Chirag Ravishankar, Jason Helge Anderson
PLDI
2009
ACM
15 years 11 months ago
A weakest precondition approach to active attacks analysis
Information flow controls can be used to protect both data confidentiality and data integrity. The certification of the security degree of a program that runs in untrusted envi...
Musard Balliu, Isabella Mastroeni
MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
15 years 11 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
OOPSLA
2009
Springer
15 years 11 months ago
Static extraction and conformance analysis of hierarchical runtime architectural structure using annotations
An object diagram makes explicit the object structures that are only implicit in a class diagram. An object diagram may be missing and must extracted from the code. Alternatively,...
Marwan Abi-Antoun, Jonathan Aldrich
SIGMETRICS
2009
ACM
165views Hardware» more  SIGMETRICS 2009»
15 years 11 months ago
Understanding intrinsic characteristics and system implications of flash memory based solid state drives
Flash Memory based Solid State Drive (SSD) has been called a “pivotal technology” that could revolutionize data storage systems. Since SSD shares a common interface with the t...
Feng Chen, David A. Koufaty, Xiaodong Zhang