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DATE
2005
IEEE
96views Hardware» more  DATE 2005»
15 years 7 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
ISVLSI
2005
IEEE
101views VLSI» more  ISVLSI 2005»
15 years 7 months ago
eWatch: Context Sensitive System Design Case Study
In this paper, we introduce a novel context sensitive system design paradigm. Multiple sensors/ computational architecture, in the form of our eWatch device, is used to infer the ...
Asim Smailagic, Daniel P. Siewiorek, Uwe Maurer, A...
INFOCOM
2010
IEEE
15 years 3 days ago
Design and Analysis of a Robust Pipelined Memory System
Abstract—Many network processing applications require wirespeed access to large data structures or a large amount of flowlevel data, but the capacity of SRAMs is woefully inadeq...
Hao Wang, Haiquan (Chuck) Zhao, Bill Lin, Jun Xu
CHI
2009
ACM
16 years 2 months ago
From interaction to trajectories: designing coherent journeys through user experiences
The idea of interactional trajectories through interfaces has emerged as a sensitizing concept from recent studies of tangible interfaces and interaction in museums and galleries....
Steve Benford, Gabriella Giannachi, Boriana Koleva...
CHI
2005
ACM
16 years 2 months ago
Design requirements for more flexible structured editors from a study of programmers' text editing
A detailed study of Java programmers' text editing found that the full flexibility of unstructured text was not utilized for the vast majority of programmers' character-...
Andrew Jensen Ko, Htet Htet Aung, Brad A. Myers