43 search results - page 7 / 9 » On Applying Incremental Satisfiability to Delay Fault Testin... |
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
ITC
2002
IEEE
15 years 2 months ago
2002
IEEE
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
VTS
2008
IEEE
15 years 4 months ago
2008
IEEE
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
DAC
2006
ACM
14 years 11 months ago
2006
ACM
Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving ...
97
Voted
ASWEC
2009
IEEE
14 years 7 months ago
2009
IEEE
Failure of a design to satisfy a system's requirements can result in schedule and cost overruns. When using current approaches, ensuring requirements are satisfied is often d...