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» On Bounded-Weight Error-Correcting Codes
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ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
15 years 6 months ago
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan ...
ICASSP
2011
IEEE
14 years 1 months ago
Analog joint source-channel Multiple Description coding scheme over AWGN parallel channels
We propose a low complexity analog joint source channel coding Multiple Description (MD) scheme for transmitting the symbols of a Gaussian source across a pair of independent AWGN...
Aitor Erdozain, Pedro M. Crespo, Baltasar Beferull...
ICASSP
2011
IEEE
14 years 1 months ago
Efficient iterative receiver for bit-Interleaved Coded Modulation according to the DVB-T2 standard
Bit-Interleaved Coded Modulation (BICM) offers a significant improvement in error correcting performance for coded modulations over fading channels compared to the previously exis...
Meng Li, Charbel Abdel Nour, Christophe Jég...
ISCA
2011
IEEE
522views Hardware» more  ISCA 2011»
14 years 1 months ago
CPPC: correctable parity protected cache
Due to shrinking feature sizes processors are becoming more vulnerable to soft errors. Write-back caches are particularly vulnerable since they hold dirty data that do not exist i...
Mehrtash Manoochehri, Murali Annavaram, Michel Dub...
VTS
2007
IEEE
203views Hardware» more  VTS 2007»
15 years 3 months ago
Multiple Bit Upset Tolerant Memory Using a Selective Cycle Avoidance Based SEC-DED-DAEC Code
Conventional error correcting code (ECC) schemes used in memories and caches cannot correct double bit errors caused by a single event upset (SEU). As memory density increases, mu...
Avijit Dutta, Nur A. Touba